1. Field of the Invention
The present invention relates to a solid-state image pickup device, and particularly relates to a MOS solid-state image pickup device and a manufacturing method thereof.
2. Description of the Background Art
A solid-state image pickup device having an amplifying MOS transistor (hereinafter, referred to as a MOS solid-state image pickup device) has a photodiode and MOS transistor for each pixel, and, by using the MOS transistor, amplifies a signal detected by the photodiode. A quality of an image taken by the MOS solid-state image pickup device is similar to that of an image taken by a solid-state image pickup device having a CCD (Charge Coupled Device) (hereinafter, referred to as a CCD solid-state image pickup device). Further, by having a CMOS circuit, the MOS solid-state image pickup device consumes less power than the CCD solid-state image pickup device. Moreover, unlike the CCD solid-state image pickup device, the MOS solid-state image pickup device has an advantage that peripheral circuits and pixels of the device, which peripheral circuits are formed near a pixel region, can be manufactured by a same CMOS process.
In recent years, elements of a solid-state image pickup device have been reduced in size, whereby a space occupied by each photodiode of the device has decreased. As a result, it has become difficult to secure a sufficient number of saturated electrons stored in each photodiode. In order to solve this problem, there is a method in which a diffusion layer, in which a photodiode is formed, is deeply formed so as to secure the sufficient number of saturated electrons. However, since a power supply voltage of each transistor of the MOS solid-state image pickup device is low, image signal charge stored in the photodiode cannot be entirely read, and as a result, the image signal charge remains in the photodiode. This consequently causes a problem of residual image. For this reason, a voltage boosting circuit is provided, which boosts voltages of gate electrodes of a transfer transistor and reset transistor of the MOS solid-state image pickup device, such that the voltages become higher than an external power supply voltage of the MOS solid-state image pickup device. This allows the image signal charge stored in the photodiode to be entirely read, and prevents the image signal charge from remaining in the photodiode. As a result, the sufficient number of saturated electrons in the photodiode is secured, and the occurrence of residual image is inhibited.
FIG. 9 shows an example of the above-described MOS solid-state image pickup device having a voltage boosting circuit. As shown in FIG. 9, the MOS solid-state image pickup device comprises shift registers 10, a multiplexer 11, a voltage conversion circuit 12 (voltage boosting circuit) including a charge pump circuit, a pixel region 13, and row selection signal lines 14. Here, the shift registers 10, multiplexer 11 and voltage conversion circuit 12 are peripheral circuits of the solid-state image pickup device. In the pixel region 13, a large number of pixels are two-dimensionally arranged to form rows and lines of pixels. Each pixel comprises a photodiode, a transfer transistor which transfers image signal charge generated in the photodiode, a reset transistor, an amplifier transistor and the like. On a semiconductor substrate of the MOS solid-state image pickup device, N-Channel MOS transistors (hereinafter, referred to as NMOS) and P-Channel MOS transistors (hereinafter, referred to as PMOS) are formed. The voltage conversion circuit 12 has a CMOS transistor (hereinafter, referred to as CMOS).
Next, operations performed by the MOS solid-state image pickup device of FIG. 9 will be described. First, the shift registers 10 driven by a voltage of 3V, which is the same as an external power supply voltage, each output a signal for selecting a pixel row (hereinafter, referred to as a row selection signal) to the multiplexer 11 which is driven by a voltage of 3V. Next, when the row selection signal and a trans signal, which trans signal is inputted from the outside of the multiplexer 11, are inputted at the same time, the multiplexer 11 outputs the row selection signal to the voltage conversion circuit 12. In other words, the multiplexer 11 performs a logic operation AND for the row selection signal and trans signal. Next, after boosting the row selection signal from 3V to 5V, the voltage conversion circuit 12 inputs, via a row selection signal line 14, the row selection signal to a gate electrode of a transfer transistor of a pixel belonging to the selected row in the pixel region 13.
Note that, in the case where the MOS solid-state image pickup device does not have a voltage boosting circuit, the row selection signal outputted from the multiplexer 11 is inputted to the gate electrode of the transfer transistor via the row selection signal line 14, without being boosted.
As described above, by having a voltage boosting circuit, the conventional MOS solid-state image pickup device is able to limit the occurrence of residual image while securing the sufficient number of saturated electrons in each photodiode even if a space occupied by each photodiode is reduced. However, the conventional MOS solid-state image pickup device has a problem in that noise is transmitted to the pixel region 13 from the CMOS and the like which are components of the voltage conversion circuit 12 which is a peripheral circuit.
There are disclosed techniques to solve this problem, e.g., a technique disclosed in the Japanese Laid-Open Patent Publication No. 2004-241577. The technique disclosed by the Japanese Laid-Open Patent Publication No. 2004-241577 relates to a method for forming a N-type well of a PMOS by using a P-type semiconductor substrate. In this technique, a peripheral circuit region is surrounded by a deep N-type well such that a pixel region and the peripheral circuit region are electrically shielded from each other. This effectively reduces, in a MOS solid-state image pickup device having a voltage boosting circuit, influence from the noise which is transmitted to the pixel region from, e.g., a CMOS in the peripheral circuit region.
Generally speaking, crosstalk occurs more in the MOS solid-state image pickup device than in the CCD solid-state image pickup device, because of a pixel structure and principle of operation of the MOS solid-state image pickup device. Crosstalk is a phenomenon where signal charge (electrons) occurring in a pixel enters an adjacent pixel due to, e.g., dispersion.
FIG. 10 is a cross-sectional view showing a structure of a conventional MOS solid-state image pickup device which is capable of inhibiting crosstalk. Hereinafter, the conventional MOS solid-state image pickup device capable of inhibiting crosstalk will be described with reference to FIG. 10. As shown in FIG. 10, an N-type semiconductor substrate 101 (an N-type epitaxial layer may be included therein) has two pixel cells in an upper portion thereof. Each pixel cell includes an N-type light receiving section 117 of a photodiode, a light receiving section surface P-type region 120, gate oxide films 118 of transistors, gate electrodes 119, an element isolation section 116, and a P-type photodiode isolation region 104. A depletion layer 106 is generated around the N-type light receiving section 117. Here, in the N-type semiconductor substrate 101, a P-type well 1 is formed more deeply than the depletion layer 106. The P-type well 1 is a retrograde well which is formed such that the deeper the depth from a semiconductor substrate surface 200, the higher is impurity concentration of added impurities. This creates potential gradient within the P-type well 1. Here, a P-type high concentration impurity region 124 is a region where the impurity concentration is extremely high. The P-type high concentration impurity region 124 is formed below the N-type light receiving section 117 and the depletion layer 106, which are components of a photodiode.
With the above-described structure, electrons 107, which are generated within the depletion layer 106 by an incident light, drift due to the potential gradient within the depletion layer 106, and then gather in the N-type light receiving section 117 (i.e., N+ region). In addition, electrons 109, which are generated outside the depletion layer 106 by the incident light, can also be efficiently gathered in the N-type light receiving section 117 by the potential gradient within the P-type well 1. Moreover, since the semiconductor substrate used here is of N-type, the electrons 109 generated below the P-type high concentration impurity region 124 by the incident light are absorbed by the N-type semiconductor substrate 101. As a result, the number of electrons 109 entering an adjacent pixel due to dispersion is decreased.
Note that, in the case of a CCD solid-state image pickup device, the N-type semiconductor substrate acts as an overflow drain. For this reason, signal charge (electrons) is inhibited from entering an adjacent pixel due to dispersion, and therefore a serious problem does not occur.
FIG. 11 shows another conventional MOS solid-state image pickup device which has a voltage boosting circuit and which is capable of limiting the occurrence of crosstalk (hereinafter, simply referred to as a conventional MOS solid-state image pickup device). Hereinafter, the conventional MOS solid-state image pickup device will be described with reference to FIG. 11. The right side of FIG. 11 shows a pixel region, and the left side of FIG. 11 shows a peripheral circuit region including a PMOS forming region and NMOS forming regions by which a CMOS is structured. The CMOS is driven by a high voltage having been boosted by a voltage boosting circuit. In the pixel region, the above-described conventional MOS solid-state image pickup device (see FIG. 10) which is capable of limiting the occurrence of crosstalk is formed.
As shown in FIG. 11, the conventional MOS solid-state image pickup device comprises an N-type semiconductor substrate 114, an N-type epitaxial layer 115, a P-type well 1, an N-type light receiving section 117, P-type wells 2, an N-type well 3, element isolation sections 116, a light receiving section surface P-type region 120, source-drain regions 122 of transistors, source-drain regions 123 of a transistor, gate insulating films 118, gate electrodes 119, and sidewall spacers 121. FIG. 11 does not show interlayer dielectrics, wirings, microlenses and the like.
In each of the pixel region and the peripheral circuit region, the N-type epitaxial layer 115 is formed to be positioned above the N-type semiconductor substrate 114. Here, for example, an impurity concentration of the N-type semiconductor substrate 114 is approximately 5E14/cm3, and an impurity concentration of the N-type epitaxial layer 115 is approximately 2E14/cm3. The P-type well 1, which is a retrograde well in which an impurity concentration increases in accordance with an increase in distance from the semiconductor substrate surface 200 toward an inner part of the substrate, is formed to be positioned above the N-type epitaxial layer 115. In the pixel region, the N-type light receiving section 117 is formed within the P-type well 1, and the light receiving section surface P-type region 120 is formed to be positioned at the semiconductor substrate surface 200. The P-type wells 2, which function as NMOS wells, are respectively formed in the NMOS forming regions so as to be positioned above the P-type well 1. The N-type well 3 functioning as a PMOS well is formed to be positioned above the P-type well 1 of the PMOS forming region. Here, a thickness of the N-type well 3 is the same as that of the P-type wells 2. The source-drain regions 122 of the transistors are formed to be positioned above the P-type wells 2. The source-drain regions 123 of the transistor are formed to be positioned above the N-type well 3. In the pixel and peripheral circuit regions, the element isolation sections 116 are formed to be positioned at the semiconductor substrate surface 200, and also, the gate insulating films 118, gate electrodes 119 and sidewall spacers 121 are formed to be positioned on the semiconductor substrate surface 200.
FIGS. 12 to 14 are cross-sectional views each showing manufacturing processes of the conventional MOS solid-state image pickup device (see FIG. 11). Hereinafter, a manufacturing method of the conventional MOS solid-state image pickup device will be described with reference to FIGS. 12 to 14. FIGS. 12 to 14 each show a pixel region on the right side thereof and a peripheral circuit region on the left side thereof.
First, as shown in FIG. 12, the N-type epitaxial layer 115 is grown on the N-type semiconductor substrate 114. Next, the element isolation sections 116 are formed at a surface of the N-type epitaxial layer 115. Here, for example, an impurity concentration of the N-type semiconductor substrate 114 is approximately 5E14/cm3, and an impurity concentration of the N-type epitaxial layer (N-) 115 is approximately 2E14/cm3. Next, the N-type light receiving section 117 is formed by implanting N-type impurities into the N-type epitaxial layer 115 of the pixel region. Then, the P-type well 1 is formed to a depth deeper than that of the N-type light receiving section 117 by performing ion implantation on the N-type epitaxial layer 115. This ion implantation is performed such that implanted impurities are distributed throughout an area between the semiconductor substrate surface 200 to a deep part of the N-type epitaxial layer 115. As a result, the P-type well 1 is formed to a depth of, e.g., 2 μm to 5 μm from the semiconductor substrate surface 200. Here, if boron (B) is implanted as impurities to be added, the ion implantation is performed, for example, at an implantation energy of 1000 keV to 3500 keV with a dose amount of 1E10/cm2 to 1E12/cm2. The P-type well 1 may be formed by a plurality of times of ion implantation.
Next, as shown in FIG. 13, the P-type wells 2 are respectively formed in the NMOS forming regions by ion implantation. The P-type wells 2 are formed to a depth of, e.g., 1 μm to 1.5 μm from the semiconductor substrate surface 200. Here, if boron (B) is implanted as impurities to be added, the ion implantation is performed, for example, at an ion implantation energy of 250 keV to 500 keV with a dose amount of 1E13/cm2 to 1E14/cm2.
Next, as shown in FIG. 14, the N-type well 3 is formed in the PMOS forming region by ion implantation. The N-type well 3 is formed to a same depth as that of the P-type wells 2, e.g., to the depth of lam to 1.5 μm from the semiconductor substrate surface 200. Here, if phosphorus (P) is implanted as impurities to be added, the ion implantation is performed, for example, at an implantation energy of 500 keV to 700 keV with a dose amount of 1E13/cm2 to 1E14/cm2. Next, by performing ion implantation on a surface of each of the P-type wells 2 and N-type well 3, a channel region for controlling a threshold voltage VT of a transistor is formed on each of the NMOS forming regions and the PMOS forming region (not shown).
Next, as shown in FIG. 11, in the pixel region, in order to form a transfer transistor, the gate insulating film 118 which is composed of silicon oxide is formed, and then a gate electrode 119 which is composed of polycrystalline silicon is formed thereon. Next, the sidewall spacer 121 is formed at a side of the gate insulating film 118 and gate electrode 119. Similarly, in the peripheral circuit region, in order to form NMOSs and a PMOS, the gate insulating films 118 composed of silicon oxide are formed, and then the gate electrodes 119 composed of polycrystalline silicon are formed thereon. Next, the sidewall spacers 121 are formed at the sides of the gate insulating films 118 and gate electrodes 119. Next, the source-drain regions 122 of transistors are formed by performing N-type impurity ion implantation on a region which is within the pixel region and in which a transistor is formed, and on each of the NMOS forming regions in the peripheral circuit region. Next, the source-drain regions 123 of a transistor are formed by performing P-type impurity ion implantation on the PMOS forming region of the peripheral circuit region. Thereafter, interlayer dielectrics, wirings, microlenses and the like are formed (not shown). In the above-described method, the conventional MOS solid-state image pickup device shown in FIG. 11, which has a voltage boosting circuit and which is capable of limiting the occurrence of crosstalk, is manufactured.
However, the conventional MOS solid-state image pickup device (see FIG. 11) has the following problem. As shown in FIG. 11, the PMOS forming region which is a component of the voltage boosting circuit has a structure comprising, in descending order from the surface, the semiconductor substrate surface 200, N-type well 3, P-type well 1, N-type epitaxial layer 115 and the N-type semiconductor substrate 114. When the conventional MOS solid-state image pickup device is driven, the N-type epitaxial layer 115 and N-type semiconductor substrate 114 are grounded, and a high voltage having been boosted by the voltage boosting circuit is applied to the N-type well 3. When this high voltage is applied, there is a case where a depletion layer generated around the N-type well 3 expands in a direction of the N-type epitaxial layer 115, and eventually reaches the N-type epitaxial layer 115. In this case, there is a problem in that electric current occurs between the N-type well 3 and N-type epitaxial layer 115 (hereinafter, referred to as punch-through current).
Note that, for manufacturing a MOS solid-state image pickup device, a P-type semiconductor substrate is generally used. In this case, the problem of punch-through current between an N-type well of a PMOS and an N-type semiconductor substrate does not occur.